What is recorded here?
Integrated programmable digital spiking cores, colocated memory/computation and event-routed intercore/interchip links in a million-unit silicon system.
Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.
Scientific scope
Artificial computational units, not biological neurons or a demonstrated human brain model. Configurability is not unrestricted on-chip learning. Reported power belongs to the specified vision workload and operating conditions, not every network or a universal efficiency ratio. Off-chip scaling, finite connectivity and global discrete-time coordination remain resource constraints.
Read the original work
- A million spiking-neuron integrated circuit with a scalable communication network and interface
- IBM Research original TrueNorth publication account
This English explanation is an editorial reading view. It does not replace the complete original work or certify its science.
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People and systems
Paul A. Merolla; John V. Arthur; Rodrigo Alvarez-Icaza; Andrew S. Cassidy; Jun Sawada; Filipp Akopyan; Bryan L. Jackson; Nabil Imam; Chen Guo; Yutaka Nakamura; Bernard Brezzo; Ivan Vo; Steven K. Esser; Rathinakumar Appuswamy; Brian Taba; Arnon Amir; Myron D. Flickner; William P. Risk; Rajit Manohar; Dharmendra S. Modha
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
Research locations and affiliations
Location not yet established
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English catalogue narrative
IBM TrueNorth: scalable digital spiking-core chip
Integrated programmable digital spiking cores, colocated memory/computation and event-routed intercore/interchip links in a million-unit silicon system.
Scientific scope
Artificial computational units, not biological neurons or a demonstrated human brain model. Configurability is not unrestricted on-chip learning. Reported power belongs to the specified vision workload and operating conditions, not every network or a universal efficiency ratio. Off-chip scaling, finite connectivity and global discrete-time coordination remain resource constraints.
Reading status
This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.
People and systems
Paul A. Merolla; John V. Arthur; Rodrigo Alvarez-Icaza; Andrew S. Cassidy; Jun Sawada; Filipp Akopyan; Bryan L. Jackson; Nabil Imam; Chen Guo; Yutaka Nakamura; Bernard Brezzo; Ivan Vo; Steven K. Esser; Rathinakumar Appuswamy; Brian Taba; Arnon Amir; Myron D. Flickner; William P. Risk; Rajit Manohar; Dharmendra S. Modha
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.