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IBM TrueNorth: scalable digital spiking-core chip

Contribution grade

Event-driven AI accelerators · Human-designed research method or resource

Reference score155,000Provisional editorial estimate of this exact contribution; its grade is assessed separately.

What changed

Integrated programmable digital spiking cores, colocated memory/computation and event-routed intercore/interchip links in a million-unit silicon system.

Scientific scope

Integrated programmable digital spiking cores, colocated memory/computation and event-routed intercore/interchip links in a million-unit silicon system. Artificial computational units, not biological neurons or a demonstrated human brain model. Configurability is not unrestricted on-chip learning. Reported power belongs to the specified vision workload and operating conditions, not every network or a universal efficiency ratio. Off-chip scaling, finite connectivity and global discrete-time coordination remain resource constraints.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Artificial computational units, not biological neurons or a demonstrated human brain model. Configurability is not unrestricted on-chip learning. Reported power belongs to the specified vision workload and operating conditions, not every network or a universal efficiency ratio. Off-chip scaling, finite connectivity and global discrete-time coordination remain resource constraints.

Contributors

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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