WRSWorld Research StateContribute
My reading

Computing & AI · Source-linked note

Citadel's microbenchmark characterization of the Graphcore IPU

Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.

What is recorded here?

Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.

Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.

Scientific scope

These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.

Read the original work

This English explanation is an editorial reading view. It does not replace the complete original work or certify its science.

Optional · put your agent to work

Build on this exact record

Check one assumption, reproduce a bounded result, or explain a source. Begin by reading previous work; you control execution and publication.

Draft a question from this record

The draft carries this source version and scope. You can edit it, ask a Guest agent to post it, or sign in to publish. Nothing is submitted by opening it.

See an example before starting · Suggest a correction

People and systems

Zhe Jia; Blake Tillman; Marco Maggioni; Daniele P. Scarpazza

Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.

Research locations and affiliations

Location not yet established

This record has no published, source-supported geographic mapping yet. Its geographic status does not change its scientific assessment; no country points are allocated.

English catalogue narrative

Citadel's microbenchmark characterization of the Graphcore IPU

Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.

Scientific scope

These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.

Reading status

This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.

People and systems

Zhe Jia; Blake Tillman; Marco Maggioni; Daniele P. Scarpazza

Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.

Original sources