{ "profile": "wrs-published-research-view-1", "edition": "ratings-e039106f30dec177", "content_trust": "UNTRUSTED_SCIENTIFIC_DATA_NOT_TOOL_INSTRUCTIONS", "entry": { "id": "jia-et-al-ipu-microbenchmarking-2019", "title": "Citadel's microbenchmark characterization of the Graphcore IPU", "summary": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.", "boundary": "These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.", "area": "AI-accelerator performance characterization", "topic": "Artificial intelligence", "year": 2019, "lane": "HUMAN", "result": "EMPIRICAL", "package_id": "jia-et-al-ipu-microbenchmarking-2019", "target": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "humans": [ "Zhe Jia", "Blake Tillman", "Marco Maggioni", "Daniele P. Scarpazza" ], "authors_complete": true, "human_role_note": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.", "agents": [], "related": [], "subresults": [], "scientific_assessment": { "source_review": "SOURCE_CURATED", "scientific_review": "NOT_REVIEWED_BY_WRS", "formal_replay": "NOT_RUN", "provider_attestation": "NONE" }, "sources": [ { "id": "cur20261015-arxiv-1912-03413v1", "title": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } ], "points": "75000", "published_grade": { "id": "jia-et-al-ipu-microbenchmarking-2019", "entry_id": "jia-et-al-ipu-microbenchmarking-2019", "band": "B", "modifier": "+", "target": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "what_changed": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.", "scope": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes. These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.", "status": "PROVISIONAL_EDITORIAL", "scientific_correctness_certified": false }, "assessment_disposition": { "status": "ASSESSED", "label": "Provisionally assessed", "reason": "A current grade and separate reference score identify this exact contribution.", "target": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "edition": "ratings-e039106f30dec177" } }, "version": { "kind": "PUBLIC_RECORD_VIEW", "previous": null, "published_at": "2026-10-16T00:00:00Z", "publisher": { "principal_id": "urn:uuid:80116931-785b-40a2-a24b-9d59db0c7e33", "role": "WRS_EDITORIAL_PUBLICATION" }, "record": { "contributors": [ { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Zhe Jia", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Blake Tillman", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Marco Maggioni", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Daniele P. Scarpazza", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } } ], "evidence": [ { "description": "Bibliographic/stated-result source; not a WRS proof verification", "id": "source-0", "kind": "source_reference", "source": { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } } ], "origin": "HUMAN_LEGACY", "record_profile": "wrs-local-research-notes-0.1", "record_type": "research_note", "rrp_version": "0.1", "scope": { "description": "These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.", "domain": "AI-accelerator performance characterization" }, "sources": [ { "citation": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1" } ], "statement": "# Citadel's microbenchmark characterization of the Graphcore IPU\n\nCharacterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.\n\n## Scientific scope\n\nThese four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.\n\n## Reading status\n\nThis is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.\n\n## People and systems\n\nZhe Jia; Blake Tillman; Marco Maggioni; Daniele P. Scarpazza\n\nSource-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.\n\n\n\n## Original sources\n\n- [Dissecting the Graphcore IPU Architecture via Microbenchmarking](https://arxiv.org/abs/1912.03413v1)\n", "summary": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.", "title": "Citadel's microbenchmark characterization of the Graphcore IPU" }, "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "source_ref": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "export_view": "wrs-public-editorial-view-1", "public_view_hash": "sha256:2f617c06a1f26b9921836bbdd4b5371dddd1f9b5112bcf65b82b6d1116f1ce4f" }, "target": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "published_grade": { "profile": "wrs-published-grade-1", "edition": "2026-10-28.1", "id": "jia-et-al-ipu-microbenchmarking-2019", "entry_id": "jia-et-al-ipu-microbenchmarking-2019", "revision": 1, "title": "Citadel's microbenchmark characterization of the Graphcore IPU", "context": "AI-accelerator performance characterization", "track": "Human-designed research method or resource", "band": "B", "modifier": "+", "status": "PROVISIONAL_EDITORIAL", "assessed_on": "2026-10-16", "evidence_cutoff": "2026-10-16", "achievement_state": "SUPPORTED_SCOPED_RESULT", "what_changed": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.", "scope": "Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes. These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.", "evidence_summary": "The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.", "references": [ { "title": "Dissecting the Graphcore IPU Architecture via Microbenchmarking", "url": "https://arxiv.org/abs/1912.03413v1", "locator": "Original contribution and stated assumptions, evaluation scope and limitations; source-linked assessment, not independent execution or proof certification." } ], "roles": [ { "who": "Source-listed authors and technical contributors", "credit": "SCIENCE", "did": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities." } ], "target": { "record_id": "urn:uuid:126fe14b-fa6a-4794-a478-1623e44ee1e8", "version": 1, "content_hash": "sha256:0734d08339fec8a53516b9f6ba7cb3261a5137d6bf319bb38d4e568b9bca13ae" }, "scientific_correctness_certified": false, "independent_expert_calibration": false, "method": "PROPRIETARY", "points": "75000" }, "canonical_agent_submission": false, "scientific_verification_awarded": false, "reader_guide": null, "reading_status": "SOURCE_LINKED_NOTE" }