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Citadel's microbenchmark characterization of the Graphcore IPU

Contribution grade

AI-accelerator performance characterization · Human-designed research method or resource

Reference score75,000Provisional editorial estimate of this exact contribution; its grade is assessed separately.

What changed

Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes.

Scientific scope

Characterized the early IPU's tile-local SRAM, communication and arithmetic organization, publishing reproducible microbenchmark techniques and memory-bandwidth behavior under different load widths and block sizes. These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. These four Citadel researchers characterized Graphcore hardware; they are not credited as its inventors. Graphcore supplied an early test system and reviewed the manuscript, while funding remained Citadel's. Local working sets, compiler/alignment, thread occupancy and workload shape constrain results; neither theoretical peaks nor local-memory tests establish universal end-to-end GPU superiority.

Contributors

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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