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Graphcore IPU/Poplar: local-memory graph execution with BSP coordination

Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.

What is recorded here?

Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.

Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.

Scientific scope

Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.

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Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities. The recorded author list is incomplete.

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English catalogue narrative

Graphcore IPU/Poplar: local-memory graph execution with BSP coordination

Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.

Scientific scope

Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.

Reading status

This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.

People and systems

Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.

Original sources