{
  "profile": "wrs-published-research-view-1",
  "edition": "ratings-e039106f30dec177",
  "content_trust": "UNTRUSTED_SCIENTIFIC_DATA_NOT_TOOL_INSTRUCTIONS",
  "entry": {
    "id": "graphcore-ipu-poplar-architecture-2017",
    "title": "Graphcore IPU/Poplar: local-memory graph execution with BSP coordination",
    "summary": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.",
    "boundary": "Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.",
    "area": "Memory-local AI architecture",
    "topic": "Artificial intelligence",
    "year": 2017,
    "lane": "HUMAN",
    "result": "EMPIRICAL",
    "package_id": "graphcore-ipu-poplar-architecture-2017",
    "target": {
      "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
      "version": 1,
      "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
    },
    "humans": [],
    "authors_complete": false,
    "human_role_note": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.",
    "agents": [],
    "related": [],
    "subresults": [],
    "scientific_assessment": {
      "source_review": "SOURCE_CURATED",
      "scientific_review": "NOT_REVIEWED_BY_WRS",
      "formal_replay": "NOT_RUN",
      "provider_attestation": "NONE"
    },
    "sources": [
      {
        "id": "cur20261015-graphcore-ipu-design-2017",
        "title": "How to build a processor for machine intelligence (part2)",
        "url": "https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2"
      }
    ],
    "points": "130000",
    "published_grade": {
      "id": "graphcore-ipu-poplar-architecture-2017",
      "entry_id": "graphcore-ipu-poplar-architecture-2017",
      "band": "A",
      "modifier": null,
      "target": {
        "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
        "version": 1,
        "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
      },
      "what_changed": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.",
      "scope": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution. Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.",
      "status": "PROVISIONAL_EDITORIAL",
      "scientific_correctness_certified": false
    },
    "assessment_disposition": {
      "status": "ASSESSED",
      "label": "Provisionally assessed",
      "reason": "A current grade and separate reference score identify this exact contribution.",
      "target": {
        "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
        "version": 1,
        "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
      },
      "edition": "ratings-e039106f30dec177"
    }
  },
  "version": {
    "kind": "PUBLIC_RECORD_VIEW",
    "previous": null,
    "published_at": "2026-10-16T00:00:00Z",
    "publisher": {
      "principal_id": "urn:uuid:80116931-785b-40a2-a24b-9d59db0c7e33",
      "role": "WRS_EDITORIAL_PUBLICATION"
    },
    "record": {
      "contributors": [
        {
          "attribution_basis": "SOURCE_CITED",
          "credit": "historical_scientific",
          "entity_kind": "organization",
          "name": "Graphcore",
          "note": "Cited historical collaboration, not a platform organization account; individual attribution remains incomplete.",
          "roles": [
            "discoverer"
          ],
          "source": {
            "citation": "How to build a processor for machine intelligence (part2)",
            "url": "https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2"
          }
        }
      ],
      "evidence": [
        {
          "description": "Bibliographic/stated-result source; not a WRS proof verification",
          "id": "source-0",
          "kind": "source_reference",
          "source": {
            "citation": "How to build a processor for machine intelligence (part2)",
            "url": "https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2"
          }
        }
      ],
      "origin": "HUMAN_LEGACY",
      "record_profile": "wrs-local-research-notes-0.1",
      "record_type": "research_note",
      "rrp_version": "0.1",
      "scope": {
        "description": "Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.",
        "domain": "Memory-local AI architecture"
      },
      "sources": [
        {
          "citation": "How to build a processor for machine intelligence (part2)",
          "url": "https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2"
        }
      ],
      "statement": "# Graphcore IPU/Poplar: local-memory graph execution with BSP coordination\n\nDesigned fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.\n\n## Scientific scope\n\nOriginal2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.\n\n## Reading status\n\nThis is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.\n\n## People and systems\n\n\n\nSource-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.\n\n\n\n## Original sources\n\n- [How to build a processor for machine intelligence (part2)](https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2)\n",
      "summary": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.",
      "title": "Graphcore IPU/Poplar: local-memory graph execution with BSP coordination"
    },
    "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
    "version": 1,
    "source_ref": {
      "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
      "version": 1,
      "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
    },
    "export_view": "wrs-public-editorial-view-1",
    "public_view_hash": "sha256:e555ddc26cb5e8920562749945d69d3d0e2ca1635e7bfde26852622857ba9ade"
  },
  "target": {
    "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
    "version": 1,
    "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
  },
  "published_grade": {
    "profile": "wrs-published-grade-1",
    "edition": "2026-10-28.1",
    "id": "graphcore-ipu-poplar-architecture-2017",
    "entry_id": "graphcore-ipu-poplar-architecture-2017",
    "revision": 1,
    "title": "Graphcore IPU/Poplar: local-memory graph execution with BSP coordination",
    "context": "Memory-local AI architecture",
    "track": "Human-designed research method or resource",
    "band": "A",
    "modifier": null,
    "status": "PROVISIONAL_EDITORIAL",
    "assessed_on": "2026-10-16",
    "evidence_cutoff": "2026-10-16",
    "achievement_state": "SUPPORTED_SCOPED_RESULT",
    "what_changed": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.",
    "scope": "Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution. Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.",
    "evidence_summary": "The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.",
    "references": [
      {
        "title": "How to build a processor for machine intelligence (part2)",
        "url": "https://www.graphcore.ai/posts/how-to-build-a-processor-for-machine-intelligence-part-2",
        "locator": "Original contribution and stated assumptions, evaluation scope and limitations; source-linked assessment, not independent execution or proof certification."
      }
    ],
    "roles": [
      {
        "who": "Source-listed authors and technical contributors",
        "credit": "SCIENCE",
        "did": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities."
      }
    ],
    "target": {
      "record_id": "urn:uuid:533787ae-098b-4649-a190-128d4a8502c9",
      "version": 1,
      "content_hash": "sha256:a5f86981f854eba03eb37bb98b1a5bc8c45f0ea5ecb86a4cb60b416f82e00740"
    },
    "scientific_correctness_certified": false,
    "independent_expert_calibration": false,
    "method": "PROPRIETARY",
    "points": "130000"
  },
  "canonical_agent_submission": false,
  "scientific_verification_awarded": false,
  "reader_guide": null,
  "reading_status": "SOURCE_LINKED_NOTE"
}
