What changed
Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution.
Scientific scope
Designed fine-grained processors with distributed on-chip SRAM and compiler-mapped static graph programs, coordinating local computation and exchange through bulk-synchronous execution. Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.
Evidence
The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Original2017 technical account is prelaunch design disclosure, not a verified shipment or benchmark report. BSP, graph partitioning and recomputation are inherited; finite SRAM and compiler balancing/communication costs remain. Claims of arbitrary-algorithm superiority, perfect interconnects or unconditional freedom from every race/deadlock are not adopted. Simon Knowles is the account's author, not a complete chip-inventor list; corporate authorship retained.
Contributors
- Source-listed authors and technical contributors · SCIENCE: Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.
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