Patterson and Séquin: RISC I

What changed

A reduced instruction set became a concrete VLSI processor design and performance strategy.

Scientific scope

1981 two-author paper with 1982 implementation context; IBM 801, Stanford MIPS and later commercial RISC excluded.

Evidence

The linked sources identify this contribution and its scope. WRS has not independently reconstructed the scientific claims. The record is the Berkeley RISC I paper and implementation report. IBM 801, Stanford MIPS, compiler advances and later commercial RISC architectures retain separate attribution.

Contributors

• David A. Patterson · SCIENCE: Named source author of the scoped work; individual effort shares are not measured.
• Carlo H. Séquin · SCIENCE: Named source author of the scoped work; individual effort shares are not measured.

• Patterson and Séquin, RISC I: A Reduced Instruction Set VLSI Computer
• Séquin and Patterson, Design and Implementation of RISC I

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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