What is recorded here?
Designed and reported a VLSI processor architecture using a deliberately small instruction set, simple control and short cycles to pursue high throughput with constrained chip resources.
Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.
Scientific scope
The record is the Berkeley RISC I paper and implementation report. IBM 801, Stanford MIPS, compiler advances and later commercial RISC architectures retain separate attribution.
Read the original work
- Patterson and Séquin, RISC I: A Reduced Instruction Set VLSI Computer
- Séquin and Patterson, Design and Implementation of RISC I
This English explanation is an editorial reading view. It does not replace the complete original work or certify its science.
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People and systems
David A. Patterson; Carlo H. Séquin
The named authors contributed to this scoped work; individual effort shares and later applications are not assigned by the byline.
Research locations and affiliations
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Documented countries / regions: United States
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English catalogue narrative
Patterson and Séquin: RISC I
Designed and reported a VLSI processor architecture using a deliberately small instruction set, simple control and short cycles to pursue high throughput with constrained chip resources.
Scientific scope
The record is the Berkeley RISC I paper and implementation report. IBM 801, Stanford MIPS, compiler advances and later commercial RISC architectures retain separate attribution.
Reading status
This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.
People and systems
David A. Patterson; Carlo H. Séquin
The named authors contributed to this scoped work; individual effort shares and later applications are not assigned by the byline.