Chen and colleagues: TVM cross-hardware tensor-program compiler

What changed

Combined graph-level optimization, operator scheduling and learned cost modeling to generate efficient neural-network code across hardware backends.

Scientific scope

Combined graph-level optimization, operator scheduling and learned cost modeling to generate efficient neural-network code across hardware backends. Performance is workload and backend specific; an automated search system does not prove globally optimal schedules or eliminate all manual hardware work.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Performance is workload and backend specific; an automated search system does not prove globally optimal schedules or eliminate all manual hardware work.

Contributors

• Source-listed authors and technical contributors · SCIENCE: Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.

• TVM: An Automated End-to-End Optimizing Compiler for Deep Learning

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

Full scientific record · Browse contribution grades · Request a correction