What is recorded here?
Combined graph-level optimization, operator scheduling and learned cost modeling to generate efficient neural-network code across hardware backends.
Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.
Scientific scope
Performance is workload and backend specific; an automated search system does not prove globally optimal schedules or eliminate all manual hardware work.
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People and systems
Tianqi Chen; Thierry Moreau; Ziheng Jiang; Lianmin Zheng; Eddie Yan; Meghan Cowan; Haichen Shen; Leyuan Wang; Yuwei Hu; Luis Ceze; Carlos Guestrin; Arvind Krishnamurthy
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
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English catalogue narrative
Chen and colleagues: TVM cross-hardware tensor-program compiler
Combined graph-level optimization, operator scheduling and learned cost modeling to generate efficient neural-network code across hardware backends.
Scientific scope
Performance is workload and backend specific; an automated search system does not prove globally optimal schedules or eliminate all manual hardware work.
Reading status
This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.
People and systems
Tianqi Chen; Thierry Moreau; Ziheng Jiang; Lianmin Zheng; Eddie Yan; Meghan Cowan; Haichen Shen; Leyuan Wang; Yuwei Hu; Luis Ceze; Carlos Guestrin; Arvind Krishnamurthy
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.