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DianNao: memory-aware compact neural-network accelerator

Contribution grade

Neural-accelerator architecture · Human-designed research method or resource

Reference score155,000Provisional editorial estimate of this exact contribution; its grade is assessed separately.

What changed

Co-designed pipelined neural arithmetic with separate input/output/weight buffers and locality-aware tiling, reporting a compact65nm post-layout inference accelerator including external-memory cost analysis.

Scientific scope

Co-designed pipelined neural arithmetic with separate input/output/weight buffers and locality-aware tiling, reporting a compact65nm post-layout inference accelerator including external-memory cost analysis. Original ICT–Inria academic work, not retroactively a Cambricon company product or the invention of every neural accelerator. Results are synthesized/place-and-route and simulated workload analyses, not a fabricated production chip or independently replayed measurement. Supports the studied feedforward convolution/classifier/pooling workloads; training was future work. Accuracy and speed depend on fixed-point choice, memory traffic and selected layers.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Original ICT–Inria academic work, not retroactively a Cambricon company product or the invention of every neural accelerator. Results are synthesized/place-and-route and simulated workload analyses, not a fabricated production chip or independently replayed measurement. Supports the studied feedforward convolution/classifier/pooling workloads; training was future work. Accuracy and speed depend on fixed-point choice, memory traffic and selected layers.

Contributors

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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