What changed
Co-designed pipelined neural arithmetic with separate input/output/weight buffers and locality-aware tiling, reporting a compact65nm post-layout inference accelerator including external-memory cost analysis.
Scientific scope
Co-designed pipelined neural arithmetic with separate input/output/weight buffers and locality-aware tiling, reporting a compact65nm post-layout inference accelerator including external-memory cost analysis. Original ICT–Inria academic work, not retroactively a Cambricon company product or the invention of every neural accelerator. Results are synthesized/place-and-route and simulated workload analyses, not a fabricated production chip or independently replayed measurement. Supports the studied feedforward convolution/classifier/pooling workloads; training was future work. Accuracy and speed depend on fixed-point choice, memory traffic and selected layers.
Evidence
The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Original ICT–Inria academic work, not retroactively a Cambricon company product or the invention of every neural accelerator. Results are synthesized/place-and-route and simulated workload analyses, not a fabricated production chip or independently replayed measurement. Supports the studied feedforward convolution/classifier/pooling workloads; training was future work. Accuracy and speed depend on fixed-point choice, memory traffic and selected layers.
Contributors
- Source-listed authors and technical contributors · SCIENCE: Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.
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