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TPU systems: systolic inference, training supercomputers and reconfigurable interconnects

Contribution grade

Machine-learning accelerator architecture · Human-designed research method or resource

Reference score340,000Provisional editorial estimate of this exact contribution; its grade is assessed separately.

What changed

Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores.

Scientific scope

Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.

Contributors

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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