AWhat changed
Developed RISC-V-controlled processing-element arrays and memory-aware recommendation inference systems; later MTIA300 added network chiplets and near-memory collective engines for communication-heavy training.
Scientific scope
Developed RISC-V-controlled processing-element arrays and memory-aware recommendation inference systems; later MTIA300 added network chiplets and near-memory collective engines for communication-heavy training. This family combines separately authored chip generations; the named contributors are associated with their respective source reports. MTIA2i co-design and MTIA300 collective offloading address different workloads. Small-message performance, eager execution, numerical parity and format support remain limitations. Reported cost and throughput comparisons depend on configuration. Later roadmap announcements are not additional realized achievements.
Evidence
The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. This family combines separately authored chip generations; the named contributors are associated with their respective source reports. MTIA2i co-design and MTIA300 collective offloading address different workloads. Small-message performance, eager execution, numerical parity and format support remain limitations. Reported cost and throughput comparisons depend on configuration. Later roadmap announcements are not additional realized achievements.
Contributors
- Source-listed authors and technical contributors · SCIENCE: Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
- MTIA: First Generation Silicon Targeting Meta's Recommendation Systems
- Meta's Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences
- MTIA300: Meta's First Training Chip Featuring Built-in NICs and Collective Offloading Engines
Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.
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