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Cerebras wafer-scale AI compute and systems co-design

Contribution grade

Wafer-scale AI computing · Human-designed research method or resource

Reference score180,000Provisional editorial estimate of this exact contribution; its grade is assessed separately.

What changed

Combined wafer-scale sparse compute, distributed on-wafer SRAM and a programmable mesh with custom power delivery, cooling and graph compilation in the WSE/CS system family.

Scientific scope

Combined wafer-scale sparse compute, distributed on-wafer SRAM and a programmable mesh with custom power delivery, cooling and graph compilation in the WSE/CS system family. Bundles2019 WSE and2021 WSE-2/CS-2 systems rather than counting every chip generation. Provider-reported architecture, capacity and performance are not independent comparisons; models must fit or use explicit partitioning/streaming. Claims of supporting every neural algorithm, universal GPU inferiority or unlimited model residence are not adopted. Corporate authorship retained without attributing the chip to release-page writers.

Evidence

The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. Bundles2019 WSE and2021 WSE-2/CS-2 systems rather than counting every chip generation. Provider-reported architecture, capacity and performance are not independent comparisons; models must fit or use explicit partitioning/streaming. Claims of supporting every neural algorithm, universal GPU inferiority or unlimited model residence are not adopted. Corporate authorship retained without attributing the chip to release-page writers.

Contributors

Provisional WRS assessment, edition 2026-10-16.1. Independent expert calibration is pending. This grade does not certify correctness or assign ownership.

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