What is recorded here?
Combined asynchronous spike routing, local synaptic state and programmable learning engines; the Loihi2 extension added microcoded state dynamics, graded spikes and richer connectivity for streaming computation.
Source-linked catalogue note. A detailed explanatory guide has not yet been prepared for this entry.
Scientific scope
One architecture family with separate2018/2021 bylines. Core memory, fan-in/fan-out and mapping limits apply; deadlock-freedom requires management activity restricted to the specified synchronization phase. Loihi2 examples in the2021 paper are hardware-constrained simulations, not measured silicon speed/energy. No biological modelling or medical outcome is catalogued; approximate sparse-coding gains do not imply superiority at arbitrary numerical tolerance.
Read the original work
- Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
- Efficient Neuromorphic Signal Processing with Loihi 2
This English explanation is an editorial reading view. It does not replace the complete original work or certify its science.
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People and systems
Mike Davies; Narayan Srinivasa; Tsung-Han Lin; Gautham Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios Dimou; Prasad Joshi; Nabil Imam; Shweta Jain; Yuyun Liao; Chit-Kwan Lin; Andrew Lines; Ruokun Liu; Deepak Mathaikutty; Steve McCoy; Arnab Paul; Jonathan Tse; Guruguhanathan Venkataramanan; Yi-Hsin Weng; Andreas Wild; Yoonseok Yang; Hong Wang; Garrick Orchard; E. Paxon Frady; Daniel Ben Dayan Rubin; Sophia Sanborn; Sumit Bam Shrestha; Friedrich T. Sommer
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.
Research locations and affiliations
Location not yet established
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English catalogue narrative
Intel Loihi: programmable event-driven spiking compute and learning
Combined asynchronous spike routing, local synaptic state and programmable learning engines; the Loihi2 extension added microcoded state dynamics, graded spikes and richer connectivity for streaming computation.
Scientific scope
One architecture family with separate2018/2021 bylines. Core memory, fan-in/fan-out and mapping limits apply; deadlock-freedom requires management activity restricted to the specified synchronization phase. Loihi2 examples in the2021 paper are hardware-constrained simulations, not measured silicon speed/energy. No biological modelling or medical outcome is catalogued; approximate sparse-coding gains do not imply superiority at arbitrary numerical tolerance.
Reading status
This is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.
People and systems
Mike Davies; Narayan Srinivasa; Tsung-Han Lin; Gautham Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios Dimou; Prasad Joshi; Nabil Imam; Shweta Jain; Yuyun Liao; Chit-Kwan Lin; Andrew Lines; Ruokun Liu; Deepak Mathaikutty; Steve McCoy; Arnab Paul; Jonathan Tse; Guruguhanathan Venkataramanan; Yi-Hsin Weng; Andreas Wild; Yoonseok Yang; Hong Wang; Garrick Orchard; E. Paxon Frady; Daniel Ben Dayan Rubin; Sophia Sanborn; Sumit Bam Shrestha; Friedrich T. Sommer
Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.