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      "statement": "# Cambricon: load-store instruction set for diverse neural workloads\n\nSpecified scalar/vector/matrix, logical, control and transfer instructions with programmer-visible scratchpads, allowing multiple neural-network techniques to share a compact accelerator ISA.\n\n## Scientific scope\n\nInherits RISC/load-store, vector operations and prior NN accelerators. The evaluation covers ten chosen neural techniques and a65nm implementation prototype, not all future networks or identical latency/energy on every workload. Operands remain bounded by scratchpad capacity and larger operations require compiler tiling. Cambricon affiliation does not retroactively turn the earlier ICT–Inria DianNao work into a company product.\n\n## Reading status\n\nThis is a source-linked WRS catalogue note. A full explanatory guide and independent scientific reconstruction have not been completed for this entry. Read the identified original work for its complete narrative and arguments.\n\n## People and systems\n\nShaoli Liu; Zidong Du; Jinhua Tao; Dong Han; Tao Luo; Yuan Xie; Yunji Chen; Tianshi Chen\n\nSource-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.\n\n\n\n## Original sources\n\n- [Cambricon: An Instruction Set Architecture for Neural Networks](https://reconfigdeeplearning.wordpress.com/wp-content/uploads/2017/02/2016-isca_cambricon-an-instruction-set-architecture-for-neural-networks_cyj.pdf)\n",
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        "title": "Cambricon: An Instruction Set Architecture for Neural Networks",
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