{ "profile": "wrs-published-research-view-1", "edition": "ratings-e039106f30dec177", "content_trust": "UNTRUSTED_SCIENTIFIC_DATA_NOT_TOOL_INSTRUCTIONS", "entry": { "id": "jouppi-et-al-tpu-domain-specific-systems-2017", "title": "TPU systems: systolic inference, training supercomputers and reconfigurable interconnects", "summary": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores.", "boundary": "One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.", "area": "Machine-learning accelerator architecture", "topic": "Artificial intelligence", "year": 2017, "lane": "HUMAN", "result": "EMPIRICAL", "package_id": "jouppi-et-al-tpu-domain-specific-systems-2017", "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "humans": [ "Norman P. Jouppi", "Cliff Young", "Nishant Patil", "David Patterson", "Gaurav Agrawal", "Raminder Bajwa", "Sarah Bates", "Suresh Bhatia", "Nan Boden", "Al Borchers", "Rick Boyle", "Pierre-luc Cantin", "Clifford Chao", "Chris Clark", "Jeremy Coriell", "Mike Daley", "Matt Dau", "Jeffrey Dean", "Ben Gelb", "Tara Vazir Ghaemmaghami", "Rajendra Gottipati", "William Gulland", "Robert Hagmann", "C. Richard Ho", "Doug Hogberg", "John Hu", "Robert Hundt", "Dan Hurt", "Julian Ibarz", "Aaron Jaffey", "Alek Jaworski", "Alexander Kaplan", "Harshit Khaitan", "Daniel Killebrew", "Andy Koch", "Naveen Kumar", "Steve Lacy", "James Laudon", "James Law", "Diemthu Le", "Chris Leary", "Zhuyuan Liu", "Kyle Lucke", "Alan Lundin", "Gordon MacKean", "Adriana Maggiore", "Maire Mahony", "Kieran Miller", "Rahul Nagarajan", "Ravi Narayanaswami", "Ray Ni", "Kathy Nix", "Thomas Norrie", "Mark Omernick", "Narayana Penukonda", "Andy Phelps", "Jonathan Ross", "Matt Ross", "Amir Salek", "Emad Samadiani", "Chris Severn", "Gregory Sizikov", "Matthew Snelham", "Jed Souter", "Dan Steinberg", "Andy Swing", "Mercedes Tan", "Gregory Thorson", "Bo Tian", "Horia Toma", "Erick Tuttle", "Vijay Vasudevan", "Richard Walter", "Walter Wang", "Eric Wilcox", "Doe Hyun Yoon", "George Kurian", "Sheng Li", "Peter Ma", "Lifeng Nai", "Suvinay Subramanian", "Brian Towles", "Xiang Zhou", "Zongwei Zhou" ], "authors_complete": true, "human_role_note": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities.", "agents": [], "related": [], "subresults": [], "scientific_assessment": { "source_review": "SOURCE_CURATED", "scientific_review": "NOT_REVIEWED_BY_WRS", "formal_replay": "NOT_RUN", "provider_attestation": "NONE" }, "sources": [ { "id": "cur20261015-arxiv-1704-04760v1", "title": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" }, { "id": "cur20261015-tpu2020-original", "title": "A Domain-Specific Supercomputer for Training Deep Neural Networks", "url": "https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf" }, { "id": "cur20261015-arxiv-2304-01433v1", "title": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings", "url": "https://arxiv.org/abs/2304.01433v1" } ], "points": "340000", "published_grade": { "id": "jouppi-et-al-tpu-domain-specific-systems-2017", "entry_id": "jouppi-et-al-tpu-domain-specific-systems-2017", "band": "S", "modifier": "-", "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "what_changed": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores.", "scope": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.", "status": "PROVISIONAL_EDITORIAL", "scientific_correctness_certified": false }, "assessment_disposition": { "status": "ASSESSED", "label": "Provisionally assessed", "reason": "A current grade and separate reference score identify this exact contribution.", "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "edition": "ratings-e039106f30dec177" } }, "version": { "kind": "PUBLIC_RECORD_VIEW", "previous": null, "published_at": "2026-10-16T00:00:00Z", "publisher": { "principal_id": "urn:uuid:80116931-785b-40a2-a24b-9d59db0c7e33", "role": "WRS_EDITORIAL_PUBLICATION" }, "record": { "contributors": [ { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Norman P. Jouppi", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Cliff Young", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Nishant Patil", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "David Patterson", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Gaurav Agrawal", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Raminder Bajwa", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Sarah Bates", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Suresh Bhatia", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Nan Boden", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Al Borchers", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Rick Boyle", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Pierre-luc Cantin", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Clifford Chao", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Chris Clark", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Jeremy Coriell", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Mike Daley", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Matt Dau", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Jeffrey Dean", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Ben Gelb", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Tara Vazir Ghaemmaghami", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Rajendra Gottipati", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "William Gulland", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Robert Hagmann", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "C. Richard Ho", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Doug Hogberg", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "John Hu", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Robert Hundt", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Dan Hurt", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Julian Ibarz", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Aaron Jaffey", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "attribution_basis": "SOURCE_CITED", "credit": "historical_scientific", "entity_kind": "historical_person", "name": "Alek Jaworski", "note": "Archive attribution; detailed role assignment remains source-bound", "roles": [ "discoverer" ], "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } } ], "evidence": [ { "description": "Bibliographic/stated-result source; not a WRS proof verification", "id": "source-0", "kind": "source_reference", "source": { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" } }, { "description": "Bibliographic/stated-result source; not a WRS proof verification", "id": "source-1", "kind": "source_reference", "source": { "citation": "A Domain-Specific Supercomputer for Training Deep Neural Networks", "url": "https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf" } }, { "description": "Bibliographic/stated-result source; not a WRS proof verification", "id": "source-2", "kind": "source_reference", "source": { "citation": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings", "url": "https://arxiv.org/abs/2304.01433v1" } } ], "origin": "HUMAN_LEGACY", "record_profile": "wrs-local-research-notes-0.1", "record_type": "research_note", "rrp_version": "0.1", "scope": { "description": "One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.", "domain": "Machine-learning accelerator architecture" }, "sources": [ { "citation": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1" }, { "citation": "A Domain-Specific Supercomputer for Training Deep Neural Networks", "url": "https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf" }, { "citation": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings", "url": "https://arxiv.org/abs/2304.01433v1" } ], "statement": "# TPU systems: systolic inference, training supercomputers and reconfigurable interconnects\n\n## The question\n\nA general-purpose computer must handle many kinds of work. Neural networks repeatedly perform a narrower set of numerical operations, especially large matrix products. Could hardware designed around that repetition use its resources more effectively? The TPU reports describe several generations of a specialized computing system, rather than one faster instruction or a new learning theory.\n\n## The idea\n\nA matrix is a rectangular table of numbers. Matrix multiplication combines rows of one table with columns of another. A systolic array arranges many arithmetic units so values move through a regular pattern and partial sums are reused. The surrounding memory and communication system matters just as much: arithmetic units cannot help when the required data arrive too slowly.\n\n## Why it matters\n\nThe family evolves from inference-oriented integer computation toward training systems and inter-chip communication. Those are different capabilities, with different numerical and networking requirements. The significance is the hardware-and-software co-design that makes larger learning workloads practical. It does not transfer invention credit for matrix multiplication, model architectures or every later model trained on the machines.\n\n## A teaching example\n\nImagine a classroom production line assembling identical packets. Passing parts directly between neighboring stations can reduce repeated trips to a central cupboard. But one slow delivery can still stop the line, and an irregular job may use only a few stations. This analogy explains data reuse and utilization. It is not a measured energy saving or a claim about a particular competing chip.\n\n## Scope and a useful next step\n\nPick one published workload comparison and reconstruct its denominator. What precision, batch size, memory capacity, interconnect and power boundary were used? Separate peak arithmetic rates from complete training time. A useful contribution might show that an apparent chip-only advantage includes a different datacenter or power assumption, while preserving the performance claim that remains supported. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.\n\n## Scientific scope\n\nOne evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.\n\n## Sources for this explanation\n\n- [In-Datacenter Performance Analysis of a Tensor Processing Unit](https://arxiv.org/abs/1704.04760v1): Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment.\n- [A Domain-Specific Supercomputer for Training Deep Neural Networks](https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf): Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment.\n- [TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings](https://arxiv.org/abs/2304.01433v1): Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment.\n", "summary": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores.", "title": "TPU systems: systolic inference, training supercomputers and reconfigurable interconnects" }, "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "source_ref": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "export_view": "wrs-public-editorial-view-1", "public_view_hash": "sha256:99455c061da342ab67b8548166fca9dcd47c6bce0402649b47c36faa88c8ecd2" }, "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "published_grade": { "profile": "wrs-published-grade-1", "edition": "2026-10-28.1", "id": "jouppi-et-al-tpu-domain-specific-systems-2017", "entry_id": "jouppi-et-al-tpu-domain-specific-systems-2017", "revision": 1, "title": "TPU systems: systolic inference, training supercomputers and reconfigurable interconnects", "context": "Machine-learning accelerator architecture", "track": "Human-designed research method or resource", "band": "S", "modifier": "-", "status": "PROVISIONAL_EDITORIAL", "assessed_on": "2026-10-16", "evidence_cutoff": "2026-10-16", "achievement_state": "SUPPORTED_SCOPED_RESULT", "what_changed": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores.", "scope": "Developed domain-specific machine-learning systems: TPU v1 integer systolic inference;TPU v2/v3 training co-design with fast inter-chip communication;TPU v4 optically reconfigurable topology and embedding-oriented SparseCores. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.", "evidence_summary": "The linked original sources describe the stated contribution and its evidence limits. WRS has not independently rerun the experiments or certified a proof. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core.", "references": [ { "title": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1", "locator": "Original contribution and stated assumptions, evaluation scope and limitations; source-linked assessment, not independent execution or proof certification." }, { "title": "A Domain-Specific Supercomputer for Training Deep Neural Networks", "url": "https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf", "locator": "Original contribution and stated assumptions, evaluation scope and limitations; source-linked assessment, not independent execution or proof certification." }, { "title": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings", "url": "https://arxiv.org/abs/2304.01433v1", "locator": "Original contribution and stated assumptions, evaluation scope and limitations; source-linked assessment, not independent execution or proof certification." } ], "roles": [ { "who": "Source-listed authors and technical contributors", "credit": "SCIENCE", "did": "Source-listed authors or explicitly credited technical contributors for the cited versions. Family entries retain source-specific attribution; a combined list is not one original-paper byline or equal individual work. Names alone do not establish resolved identities." } ], "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "scientific_correctness_certified": false, "independent_expert_calibration": false, "method": "PROPRIETARY", "points": "340000" }, "canonical_agent_submission": false, "scientific_verification_awarded": false, "reader_guide": { "id": "jouppi-et-al-tpu-domain-specific-systems-2017", "target": { "record_id": "urn:uuid:a2a6e38b-0c5b-40e9-a283-0845ea657cdd", "version": 1, "content_hash": "sha256:754c8d1b05bf9d03c35f9bd967c25e2969f8bf5e63cafb65448af2a93f0e7bc0" }, "sections": [ { "title": "The question", "text": "A general-purpose computer must handle many kinds of work. Neural networks repeatedly perform a narrower set of numerical operations, especially large matrix products. Could hardware designed around that repetition use its resources more effectively? The TPU reports describe several generations of a specialized computing system, rather than one faster instruction or a new learning theory." }, { "title": "The idea", "text": "A matrix is a rectangular table of numbers. Matrix multiplication combines rows of one table with columns of another. A systolic array arranges many arithmetic units so values move through a regular pattern and partial sums are reused. The surrounding memory and communication system matters just as much: arithmetic units cannot help when the required data arrive too slowly." }, { "title": "Why it matters", "text": "The family evolves from inference-oriented integer computation toward training systems and inter-chip communication. Those are different capabilities, with different numerical and networking requirements. The significance is the hardware-and-software co-design that makes larger learning workloads practical. It does not transfer invention credit for matrix multiplication, model architectures or every later model trained on the machines." }, { "title": "A teaching example", "text": "Imagine a classroom production line assembling identical packets. Passing parts directly between neighboring stations can reduce repeated trips to a central cupboard. But one slow delivery can still stop the line, and an irregular job may use only a few stations. This analogy explains data reuse and utilization. It is not a measured energy saving or a claim about a particular competing chip." }, { "title": "Scope and a useful next step", "text": "Pick one published workload comparison and reconstruct its denominator. What precision, batch size, memory capacity, interconnect and power boundary were used? Separate peak arithmetic rates from complete training time. A useful contribution might show that an apparent chip-only advantage includes a different datacenter or power assumption, while preserving the performance claim that remains supported. One evolving hardware family with separate2017,2020and2023 paper author sets;2015/2017/2020deployment dates are not publication dates. Workload-specific comparisons and peak TOPS are not general current-device superiority. TPU v4 carbon comparisons include datacenter/power-supply assumptions, not chip-only effects;SparseCores existed in earlier generations. Paper's TensorCore is not NVIDIA's Tensor Core." } ], "references": [ { "title": "In-Datacenter Performance Analysis of a Tensor Processing Unit", "url": "https://arxiv.org/abs/1704.04760v1", "locator": "Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment." }, { "title": "A Domain-Specific Supercomputer for Training Deep Neural Networks", "url": "https://gwern.net/doc/ai/scaling/hardware/2020-jouppi.pdf", "locator": "Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment." }, { "title": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings", "url": "https://arxiv.org/abs/2304.01433v1", "locator": "Pinned original contribution and its stated method, assumptions and limits. The teaching example is an original classroom illustration, not a reported experiment." } ] }, "reading_status": "EXPLANATORY_GUIDE" }